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 MC10EPT20, MC100EPT20 3.3V TTL/CMOS to Differential PECL Translator
The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline 8-lead SOIC package and the single gate of the EPT20 makes it ideal for those applications where space, performance, and low power are at a premium. The 100 Series contains temperature compensation.
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* * * * * * * * * * *
390 ps Typical Propagation Delay Maximum Frequency > 1 Ghz Typical Differential 3.3 V PECL Outputs PNP TTL Inputs for Minimal Loading VCC Range of 3.0V to 3.6V ESD Protection: >1.5 KV HBM, >200 V MM, >2 KV CDM Q Output will default HIGH with inputs open Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1, Indefinite Time Out of Drypack. For Additional Information, See Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 150 devices
MARKING DIAGRAMS*
8 1 SO-8 D SUFFIX CASE 751 1 8 HPT20 ALYW 1 8 KPT20 ALYW
8 1 TSSOP-8 DT SUFFIX CASE 948R
8 HT20 ALYW 1
8 KT20 ALYW 1
NC
1
8
VCC
H = MC10 K = MC100 A = Assembly Location
L = Wafer Lot Y = Year W = Work Week
Q
2
TTL
7
D
ORDERING INFORMATION
Q 3 PECL 6 NC Device MC10EPT20D MC10EPT20DR2 NC 4 5 GND MC100EPT20D MC100EPT20DR2 MC10EPT20DT Package SO-8 SO-8 SO-8 SO-8 TSSOP-8 Shipping 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel 98 Units/Rail
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram PIN DESCRIPTION
PIN Q, Q D VCC GND NC FUNCTION Differential PECL Outputs TTL Input Positive Supply Ground No Connect
MC10EPT20DTR2 MC100EPT20DT MC100EPT20DTR2
TSSOP-8 2500 Tape & Reel TSSOP-8 98 Units/Rail
TSSOP-8 2500 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
February, 2001 - Rev. 3
Publication Order Number: MC10EPT20/D
MC10EPT20, MC100EPT20
MAXIMUM RATINGS (Note 1.)
Symbol VCC VI Iout TA Tstg JA JC JA JC Tsol Power Supply Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP Parameter Condition 1 GND = 0 V GND = 0 V Continuous Surge VI VCC Condition 2 Rating 6 6 50 100 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 265 Units V V mA mA C C C/W C/W C/W C/W C/W C/W C
1. Maximum Ratings are those values beyond which device damage may occur.
LVTTL INPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0 V; TA = -40C to +85C
Symbol IIH IIHH IIL VIK VIH VIL Characteristic Input HIGH Current (Vin = 2.7V) Input HIGH Current MAX (Vin = 6.0V) Input LOW Current (Vin = 0.5V) Input Clamp Voltage (Iin = -18mA) Input HIGH Voltage Input LOW Voltage 2.0 0.8 Min Typ Max 20 100 -0.6 -1.2 Unit A A mA V V V
10EPT PECL OUTPUT DC CHARACTERISTICS VCC = 3.3V; GND = 0V (Note 2.)
-40C Symbol
ICC
25C Max 28 2415 1615 Min 18 2230 1430 Typ 23 2355 1555 Max 28 2480 1680 Min 19 2290 1490
85C Typ 24 2415 1615 Max 29 2540 1740 Unit mA mV mV
Characteristic Power Supply Current HIGH Output HIGH Voltage (Note 3.) Output LOW Voltage (Note 3.)
Min 18 2165 1365
Typ 23 2290 1490
VOH VOL
NOTE: 10EPT circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 2. Output parameters vary 1:1 with VCC. 3. All loading with 50 ohms to VCC-2.0 volts.
100EPT PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V (Note 4.)
-40C Symbol IEE VOH VOL Characteristic Power Supply Current Output HIGH Voltage (Note 5.) Output LOW Voltage (Note 5.) Min 20 2155 1355 Typ 25 2280 1480 Max 30 2405 1605 Min 22 2155 1355 25C Typ 27 2280 1480 Max 32 2405 1605 Min 23 2155 1355 85C Typ 28 2280 1480 Max 33 2405 1605 Unit mA mV mV
NOTE: 100EPT circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 4. Output parameters vary 1:1 with VCC. 5. All loading with 50 ohms to VCC-2.0 volts.
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MC10EPT20, MC100EPT20
AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; GND = 0 V (Note 6.)
-40C Symbol fmax tPLH, tPHL tSKEW tJITTER tr tf Characteristic Maximum Frequency (See Figure 2. Fmax/JITTER) Propagation Delay to Output Differential Device-to-Device Skew (Note 7.) Cycle-to-Cycle Jitter (See Figure 2. Fmax/JITTER) Output Rise/Fall Times (20% - 80%) Q, Q 70 1 100 280 350 Min Typ Max >1 Min 25C Typ Max >1 Min 85C Typ Max >1 Unit GHz ps 430 150 <2 170 80 1 120 300 370 450 150 <2 180 90 1 140 320 400 490 170 <2 190 ps ps ps
6. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V. 7. Skew is measured between outputs under identical transitions.
900 800 700 VOLTAGE (mV) 600 500 400 300 200 100 0
9 8 7 6 5 4 3 2 1 (JITTER) 400 600 800 1000 1200 1400 1600 ps (RMS)
EEEE EEEE EEEE
0 200
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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MC10EPT20, MC100EPT20
Q Driver Device Qb 50 W 50 W
D Receiver Device Db
V TT V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020
- - - - - - - - - - -
ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
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MC10EPT20, MC100EPT20
PACKAGE DIMENSIONS
-X- A
8 5
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE V
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
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MC10EPT20, MC100EPT20
PACKAGE DIMENSIONS
TSSOP-8 DT SUFFIX CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8
5
L
1 PIN 1 IDENT 4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
-W- G DETAIL E
DIM A B C D F G K L M
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MC10EPT20, MC100EPT20
Notes
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MC10EPT20, MC100EPT20
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC10EPT20/D


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